What will computer chips look like in 2045?
In a Nutshell
Intel's process development for 14A relies on systematic yield improvement through inline metrology, end-of-line testing, and cross-section analysis to identify and eliminate defects across ~2,000 manufacturing steps. High-NA EUV tools combined with backside power architecture enable single-pass lithography for denser interconnects, while CFET transistor stacking and ruthenium interconnects represent the next architectural shifts beyond gate-all-around. However, global tool supply constraints—ASML produces fewer than 100 EUV machines annually—fundamentally limit production scaling to roughly 2X current capacity, creating a mismatch with AI's 3X annual compute demand growth.
These notes were generated by AI and may contain inaccuracies.
There's never been as big a shock to the semiconductor industry as the current surge in demand from AI. AI is driving incredible computing demand. Easily 40-50% above our maximum capacity, which I've never seen before. Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do. But the production of these chips is bottlenecked by tools that Intel buys from their suppliers.
Most famously, ASML's EUV machines. If they don't have the equipment, they can't make the chips here. I spent two days touring Intel's fabs to prepare for these interviews with its leadership. I wanted to understand what it takes to manufacture the world's most advanced chips and how hardware is shaping the future of AI. I'm joined by Chris Auth, who leads development of all the processes that are currently under manufacturing. The thing I want to understand in more concrete detail is how the development of a new process actually happens.
If 14A is going to come out in three years or two years from now, what is happening from now till then? I want you to walk me through as much detail as you can, everything from the level of "how is the yield improving?" to what kind of telemetry you guys look at? What kind of experiments do you guys run? I want to understand what is going to happen over the next two years as concretely as possible. 14A has been in development for about three-plus years at this stage, so quite a bit of pre-work has been done to get it to the stage that it's at right now.
Right now, we're getting very close to where we're finalizing the process. We're finalizing the tool sets that it will be manufactured on, and we're working on the fine-tuning of each of the process steps. There are about 2,000 steps in the factory that you have to go do. You need to do really intricate work at each one of those to make sure it's fine-tuned, it can go into manufacturing, it can run thousands of wafers a week on this process, and it can be repeatable every single time.
Right now, you might have a certain yield. Walk me through how that increases month over month. There's a line running at 14A. What happens from now till next month that will result in the yield changing? How do you identify where the defects are? How do you fix that? There's a constant process that we go through in identifying defects. There are two main ways that we'll identify them. One is we have inline metrology. We have tools that will look at the wafers and say, "Ah, there's a defect there, there's a defect there, there's a defect there." Then also at the end of line, either electrical test or we sort and see where the fails are.
We will identify failures, and then we will get analysis on those failures. We'll cross-section it. You were in the TEM lab yesterday, and you saw how you can get cross-sections. You'll get a cross-section of a defect, and from that, you'll be able to say, "Oh, that defect is between these layers, so it must have come from this section of the flow. Oh, we have inline metrology in that section, which has identified defects. Those are the defects we need to go after."
What we've learned is that you don't want to do too much innovation in one node, because the more innovation that you do, the more complex it becomes. While you'll be able to get that to work, you need to hit a certain schedule, and that's the schedule that your customer ultimately wants. Having that predictable schedule is a key piece. You've got to figure out how much innovation you can put in in order to meet the customer's requirements in the timeline that they need it.
Intel learned how costly that tradeoff can be with delays to its 10 nanometer node, whose original target launch date was 2016, but which didn't begin manufacturing until 2018. Usually Intel has been the keeper of Moore's Law, a new cadence of manufacturing every two years, but their last set of products slipped almost four years. Intel today having its worst day in four months, the stock now down more than 15%. I also want to point out Taiwan Semiconductor up 13% off of Intel's bad news.
Ten nanometer was a good example of where we had very aggressive targets. We were doing what was called hyperscaling at the time, so we were scaling much faster than what had been historically done. In order to do that, we came up with all sorts of innovative ideas on how we could achieve that without new tools, because the tools weren't ready. That put a lot of burden on the process and a lot of burden on the engineers.
Now, at the end of the day, 10 nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost, but it took us longer to do that than what we would have liked. So we've tried to take that learning into future technology nodes and say, "Hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule."
EUV was probably the big thing. When we started to define 10 nanometer, the conclusion was EUV was not ready. EUV is extreme ultraviolet lithography. It prints chip patterns with light at a wavelength of 13.5 nanometers, about 14 times shorter than that emitted by previous tools that chipmakers had relied on. The shorter the wavelength, the finer the features that a single exposure can print. But Intel decided this technology wasn't going to be ready in time.
TSMC transitioned to EUV much sooner. It put EUV into volume manufacturing in 2019 and ramped it up further on its 5nm node in 2020. Intel's first EUV process did not reach products until 2023, so TSMC had about four more years of experience with these machines.
One thing that did also come out of 10 nanometer is we started to define a set of maturity metrics. We use those maturity metrics in a process which we call phase gate, where we would say, "To go from pathfinding into development, these are the criteria that we need to go hit." There are yield criteria, defect criteria, performance criteria, and we need to hit those in order to move to the next set of the flow. If there's something that doesn't make that, then it misses that, and it goes on to the next technology. We focus on the items that are ready and we can run and put into a process, because one of the key things is staying on schedule.
Staying on schedule is hard partly because new transistor designs take decades to mature. Modern chip transistors evolved from the planar MOS transistor, demonstrated in 1960. The history of transistors since has been the progression from two dimensions into three. Each development that Chris goes on to describe, from FinFET to gate-all-around, is a step in that progression.
A transistor is basically a switch. When it's turned on, it allows current to flow between its two ends, which are called the source and the drain. A piece called a gate sits on top of the silicon between the source and the drain. Applying a positive voltage to the gate turns the switch on, because the positive voltage pulls negatively charged electrons in the silicon beneath up toward the gate. However, a thin layer of insulation stops them from actually reaching the gate. So the electrons collect just beneath that insulation and form a thin conducting path from the source to the drain. This is called the channel. Remove the voltage and the electrons disperse, the channel disappears, and the switch turns off.
As transistors shrank, the source and the drain got so close together that current could flow through the channel even when the switch was supposed to be off. We needed a better way to control the channel and prevent current from leaking through. The fix was to give the gate a tighter grip on the channel by touching it from more sides.
In the original planar transistor, the gate only touches the channel from the top. The FinFET transistor squeezes the channel into a thin vertical fin of silicon. The gate drapes over the fin, so it controls the channel from three sides. The next progression from there was to cover not only the top and the sides of the channel, but also the bottom. This technology is called gate-all-around, and it slices the channel into thin ribbons, each of which gets completely wrapped around by the gate.
But getting gate-all-around to work required new materials and new manufacturing steps. To build these floating ribbons of silicon, you first sandwich them between alternating layers of a temporary placeholder material, which holds the space where the gate will eventually go. We use a placeholder because the materials in the real gate wouldn't survive the processing that comes after, which involves baking the wafer at around 1,000 degrees Celsius. Once these hot steps are done, chipmakers etch away the placeholder, leaving the ribbons suspended. Then they fill the gaps around every ribbon with a thin coat of a special insulator called a high-k material, whose purpose is to let the gate pull more strongly on the channel. And then on top of this material, they put the metal of the gate itself.
FinFET was demonstrated in a lab in 1989 and reached volume production at Intel in 2011. A gate-all-around transistor had been demonstrated a year earlier, in 1988, but Samsung didn't begin producing gate-all-around chips until 2022. So these ideas, FinFET and gate-all-around, were developed around the same time, but they reached production a decade apart.
Gate-all-around's a good example, because back in the '90s we knew of this idea. But we knew there were going to be these problems on how you put this into high-volume manufacturing. At the same time, there are other things like high-K metal gate. There's strained silicon, there's FinFETs that are out there. It's a question of when's the right time to go and tackle those? Well, you don't want to tackle something before you have to. If you have these other things that can drive performance, you would go and do that. So we went through this path. We did strained silicon, high-K metal gate, we did FinFETs, and then it became, "Well, we need to do things further. How do we get there?" Well, gate-all-around's really the ultimate transistor out there. Maybe it's time to go and start tackling some of those issues that you have. You're right, now you have to look at how do you put high-K metal gate in with gate-all-around. It's that innovation that takes time. Sometimes you need new materials. Sometimes you need a different tool in order to be able to do some of the things that you need to go do, and that requires invention from the tool vendors.
You have to go to the tool vendor and say, "Hey, I need a tool that can do XYZ. I need a gas that can deposit this particular material that goes into that. I need a heating chuck that has this characteristic to it." All those things take time. Some of it is iterative, where you have to run a gate-all-around transistor and say, "Oh, well, that didn't work. Let me figure out what was wrong with my hypothesis and try it again with some different structure."
How has the nature of R&D changed from the era of just making planar transistors smaller and smaller and getting the benefits of Dennard scaling, to the world we're in today? Is it just a totally different kind of R&D process? Previously it was, "Let's make things smaller, smaller, smaller." Now you look at all these other facets of performance at the same time, and improvements in size don't come as easily. Walk me through whether there was some crucial change in the R&D process at that point.
If you look at the '80s and '90s, yes, it was driven really by Dennard scaling, lithography. We just made things smaller, transistors got faster, they got more reliable, and it was a very predictable cadence. When we started to hit the 2000s, we saw, "That's not good enough anymore. We need to do something different." To me, it became this golden age of innovation. For each technology node, how are you going to provide more scaling? How are you going to provide more performance? It drove things like strained silicon. It drove high-K metal gate. It drove FinFETs. It drove gate-all-around. It drove backside power. These are things that in the '80s and '90s you would be like, "Oh no, we're not touching any of that," because we just continued to have the same process flow. We just scaled it, scaled it, scaled it. But for somebody like me who's a transistor junkie, it's awesome, because now the playbook's open. You can do all sorts of things out there. You can bring in new materials. Just look at the number of materials we used to use in the '90s versus the materials today. It's probably gone up 10X. There's a lot of innovation. There's atomic layer deposition. You're controlling this stuff atom by atom. So it's changed a lot how you approach the process. Before, it was, "Try to not change anything." Now it's, "Take the sledgehammer and start tearing the thing up and come up with some new idea."
For 14A, Intel is using a new kind of lithography machine: High-NA EUV. It uses the same extreme ultraviolet light as today's EUV machines, but changes the optics. NA, or numerical aperture, is a measure of how wide a cone of light the machine's mirrors can focus onto the wafer. The wider the cone you can focus, the smaller the spot that your light can carve. Standard EUV machines have an NA of 0.33. High-NA widens it to 0.55. So High-NA can print features about 1.7 times smaller in a single pass. When features are smaller than the lithography machine can print, chipmakers have to split the pattern across several passes, each printing a different set of features. The most tightly packed patterns can require two, three, or even four passes. Each additional pass takes up valuable time on a machine that costs around $200 million, and it introduces another opportunity for defects. High-NA machines cost about twice as much, but they can reduce the number of passes that are needed. So the question which determines whether they justify their higher price is how much more time they save and how much they reduce the risk of defects.
Now you guys are using High-NA EUV tools for 14A, whereas TSMC has said that they don't make economic sense yet for them. How do you decide whether the next litho tool is the one that is ready to adopt or not? High-NA's a good example of where, because of the architecture of our technology versus TSMC's, we make different conclusions off of the same tool set. We use backside power. That means that you actually alleviate some of the pitch requirements you have on the front side. That allows you to print that directly with High-NA. TSMC has to run tighter pitches because they don't have backside power, and they can't do that with High-NA, so they have to use double patterning EUV. So for them, it is not very helpful. For us, it is very helpful.
Now at 14A, we've left it as an option, and it's something that we'll have a discussion with the customer on, because there's some value proposition to it, and there's some complexity that it adds. Chris is referring to a feature called backside power. A chip has two different kinds of wiring. Power lines deliver electricity to the transistors, and they need to be thick. Signal lines let the transistors talk to each other. They're much thinner, but they need to be spaced apart so that the signal from one wire doesn't interfere with the signal from another. In the past, all of these power lines and signal lines had to be crammed together on top of the transistors. Intel's newest process moves these power lines below the transistors, to the back of the wafer. This frees up space on top, so the signal lines don't have to be packed as tightly. This change makes High-NA worth it for Intel. Without backside power, the wiring is so tight that it would require multiple passes to print, even with High-NA. With backside power, a single High-NA pass is enough.
Outside companies can now commission Intel to manufacture chips that they've designed. They follow Intel's process design kit, or PDK: the menu of what a given process can build, and the rules for building it. Do you need to lock that into your PDK right now for customers who are planning on developing on 14A? It's an option in the PDK today, and we're handling it as a customer-by-customer discussion as to whether or not they want to go down that path or not. For 18A, there was public reporting that there were delays in or issues with the PDK, such that some instructions didn't work, and it was difficult for people to use your foundry to build their chips.
Tell me about the process of Intel becoming a foundry and then having a PDK that other customers can use to make whatever chip they're making as well. There's definitely a learning curve to how you become a foundry. That's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM. We've gone to our product teams and shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK-type process. So that's a new process that we've had to implement on 18A. 18A started out not having a PDK. There's definitely a lot of feedback we've gotten from the customers as to what they expect for quality and maturity of the PDK and what sort of information they want to see in there. We've tried to incorporate that into making sure that we have a PDK that meets our customers' requirements. That's where we've ended up. We're starting to get PDKs that have this, and 14A will have that from the get-go. It has very high quality PDKs. Again, there are maturity metrics for what is a PDK 0.5 versus a 0.9 versus a 1.0. We're constantly going through and taking customer feedback and incorporating that into the quality of our PDK.
For most of its history, Intel's fabs made only Intel's chips. That could be part of what allowed TSMC to gain an edge. Serving many customers gave TSMC more wafers to learn from, more revenue to reinvest, and more pressure to hit deadlines.
If a butterfly flapped its wings in the '60s, could you imagine a world where gate-all-around is not even a word people have heard of, an idea people are familiar with, but people are thinking of an extremely different branch of the tech tree? How far down the tech tree do you think things could be totally different? Could it be that we're not even using copper? If you look at, say, transistors and interconnects, where we've gotten to, as far as the transistor and gate-all-around and it being the ideal transistor structure, was somewhat inevitable. As I said, in the '90s we were already talking about these types of things. Backside power, that one is pretty out there. Even in the '90s, the idea that you're going to strip off the entire silicon substrate and put lines on the backside, that one is probably something that's a little bit out there. Copper, of course copper wires are the best, so I don't know how you would end up somewhere else besides copper. But you guys are exploring other— For some of the very tightest pitches, it is inevitable that you will replace copper. That's a good example of where you will have another material that will come in there. But for the larger lines, I think copper is about where it is at.
Once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime. Now you see it's not, "Hey, there's just some substrate and you stack everything on top." Now you've got a transistor which is floating in interconnect, and you're like, "Okay, well, why don't I have transistors, interconnect, a little more transistors, more interconnect?" This whole 3D stacking that we now do with just discrete chips that we stack on top of each other. Now you're like, "Why can't I just build an entire structure like this?" You see it with memory, NAND, DRAM. They have some incredible 3D structures. NAND already does it, DRAM talks about it, but I think that DRAM inevitably is going to go there too.
A lot of people say, "Oh no, we're not going to do this because we can't do it in the next five years." Well, come on, let's put a larger timescale on this. Let's put 10 years, 20 years. In 2045, do you think you could do it? Now you start to say, "Oh yeah, I could see us having some pretty exotic structures at that point." We limit ourselves by what we see as possible in the next four years. As I've always said, when people say, "How do you see technology scaling going?", we have visibility for about four years. Then you get out to the four years, and you go, "Yeah, I think there's something we can do another four years out of that." And you get to that four years, and you're like, "Yeah, I think you can do something." But if you start to talk about 10 years, it becomes hard to say what it's going to be.
Chris's idea of building upward could start with the transistors themselves. Chips use two types of transistor, called n-type and p-type, which work the same way, but with the charges reversed. Nearly every circuit is built by pairing them up. Today, chipmakers build them side by side. The next step is to stack them directly on top of each other in order to save space. In principle, that fits twice as many transistors into the same area. This design is called a CFET, short for complementary field-effect transistor. But every extra layer adds manufacturing steps and cost, and also leads to heat building up that doesn't have a clear way to escape.
Because logic consumes more power than memory, you can't do stacks of DRAM that make HBM or 3D NAND as easily with logic, because of the heat issue. Is that the fundamental issue over the long run? How you— Thermals. There are three things you have when you try to say, "Hey, what limits compute?" It's how fast can you do the switch, so the frequency of the device. How much power does it take in order to do that switch, so the power efficiency of it. The third one is, how do you dissipate the heat that was generated by doing that switch? That's the thermals piece of it. These are not new problems. You can go back 20 years and you can see articles on these three things. The question is, thermals… how do you deal with that, particularly when you start to talk about these 3D-type devices? There is a need for that sort of system-level analysis and simulation tools. I think we're in its infancy because we've just started to look at this. It is a limiter, and it will be a limiter, but again, these are problems that we can go solve. The problems respond to work, but engineering time
Engineering time and experimental wafers are finite resources at Intel, making the allocation of these across thousands of problems one of the hardest aspects of bringing up a new node. Kevin Fischer participates in Intel's Hot Topics meetings where these critical decisions are made regarding improvements to 18A and 18A-P technologies.
Engineers present different experiments and ideas for improving yield and performance, and the integration engineers determine what data is needed, how to proceed, and how to accelerate progress. The average engineer lacks visibility into how their work impacts Intel's bottom line and customer satisfaction.
"One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you've waited too long. It's already too late."
Decisions involve determining acceptable risk levels when moving to production, as this directly risks revenue and the bottom line.
During epitaxy deposition, abnormal growth occurs creating nodule-like structures that grow rapidly. These nodules cause transistors to short when one epi connects to the wrong epi, resulting in non-functional transistors.
A special clean process is being evaluated that would eliminate nodules after deposition. Parallel work is conducted on multiple potential fixes since the easiest solution isn't always evident initially.
Intel's chips have featured Processor Trace for the past decade, which records all program code execution with sufficient detail to reconstruct every function call. While most companies don't require this level of detail, Jane Street uses it to investigate specific fleeting moments in their trading systems, such as delayed responses to network packets.
A Jane Street engineer and summer intern developed magic-trace, leveraging Processor Trace output to provide a complete history of function calls leading to specific moments of interest. This bottom-up project is now used daily by traders and developers across Jane Street.
Intel uses a tiered "hot boxes" system in the factory where different grades move at different speeds. HotBox 1 provides the highest priority, racing through the factory with priority at every tool, but creates inefficiency for the overall factory operation.
This system is analogous to a highway carpool lane reserved for specific experiments, allowing them to bypass normal traffic while potentially reducing overall factory efficiency.
Jack Kavalieros demonstrated Intel's research into ruthenium as a potential replacement for copper interconnects. As copper wires shrink, they require liners for deposition, but ruthenium can be etched directly, eliminating the need for liners.
At approximately 20-nanometer pitch dimensions, ruthenium demonstrates better conductivity and resistivity than copper. The liner functions as a glue/transition layer that becomes proportionally more significant as dimensions scale down.
Intel moved from copper to cobalt at 10 nanometer, but is now reconsidering copper again. Technology selection involves evaluating multiple options and making decisions as the manufacturing timeline approaches.
The integration of materials into the complex transistor ecosystem requires evaluating both scalability and integration capability with other components.
CFET (Complementary FET) involves stacking transistors on top of each other rather than placing them side-by-side. This architecture is being evaluated not just by Intel but by competitors and external labs.
While stacking relaxes some compression constraints, it creates new challenges including vertical interconnect routing between stacked transistors. The aspect ratio for creating and filling trenches becomes increasingly difficult.
Filling challenges include potential air gaps or unfilled holes. Short-loop vehicles are used to accelerate development by testing unit cells of the process rather than completing full manufacturing cycles that take a month or longer.
Current CFET development uses simplified versions with one wire for NMOS and one wire for PMOS rather than four ribbons stacked on four ribbons. This reduces aspect ratio challenges while still enabling evaluation of device stacking and interconnection.
The lab can deposit 2D materials at atomic scale (one monolayer) and print features using EUV or E-beam technology comparable to production specifications.
The extended timeline for bringing new technologies to production results from the need to resolve thousands of steps that must work together uniquely. Materials require research into deposition, etching, removal, and compatibility with adjacent layers.
Architecture changes like CFET may seem simple but involve aspect ratio challenges for etches, depositions, and cleans that existing technology may not yet support.
Ideas fail when fundamental incompatibilities are discovered with existing processing. Initial experiments may succeed with simple depositions, but fail when attempting to make electrical contacts or when subsequent processing steps interact with the material through gaseous interactions.
Hermetic sealing becomes critical when materials aren't properly isolated from downstream processing steps.
While transistor stacking remains in research, chip stacking is already in production. Nvidia's Blackwell GPU joins two processor chips with eight stacks of high-bandwidth memory, where inter-chip communication speed often limits AI workload performance.
The area-versus-perimeter problem means doubling chip dimensions quadruples area but only doubles edge connections, creating bandwidth bottlenecks as transistors become denser.
Packaging has evolved from side-by-side chip layouts to 2.5D packaging using interposers, and now toward hybrid bonding. Hybrid bonding aligns copper interconnects of separate chips, then heats them so interconnects expand and bridge the gap while bonding insulating surfaces.
This eliminates solder bumps, enabling much denser connections. The technology is entering volume manufacturing after resolving alignment and defect challenges.
Two hybrid bonding approaches exist: wafer-to-wafer and chip-to-wafer. Wafer-to-wafer bonding requires perfectly matching dies and is popular in CMOS image sensor manufacturing, but faces yield challenges due to randomization between good and bad dies.
Chip-to-wafer bonding allows selection of known good dies tested at the chip level, bonding only known good dies to known good base positions. Both approaches will likely continue based on customer and architecture requirements.
First-level interconnect pitch has scaled from 130-150 micrometers 15 years ago to 25 micrometers today in Foveros high-volume manufacturing. Research has demonstrated 0.45 micron pitch hybrid bonded devices with proven reliability.
Interconnect layers within a single wafer are typically 1 micron to 0.5 micron in size, suggesting potential for connecting lower layers within silicon through packaging-level bonding.
Beyond AI's bandwidth advantages, hybrid bonding offers power benefits for non-AI applications including client devices. Finer interconnects reduce power consumption measured in picojoules per bit for interfaces between components like CPUs and GPUs.
This contributes to lower overall system power budgets, resulting in reduced heat generation for equivalent performance.
ASML produces fewer than 100 EUV tools per year and does not plan to significantly increase production by the end of the decade. This capacity must be shared between Intel, TSMC, and memory manufacturers like SK Hynix. The bottleneck extends beyond EUV tools to all manufacturing equipment, as once a process flow like 18A is locked in, specific tools cannot be substituted with alternatives from different suppliers.
Intel maintains fungibility between nodes, with approximately 80% of the tool set reusable when transitioning from 18A to 14A. The remaining 20% requires new capabilities for denser geometries. This approach provides flexibility when ramping production across different process nodes.
Even with unlimited capital expenditure, existing constraints limit production increases. With already high yields, each additional 1% improvement becomes extremely difficult. Global tool availability could support approximately 2X increase in leading-edge wafer production, but not 10X. This creates a fundamental mismatch with AI industry demands that have historically required 3X compute increases year-over-year.
A couple billion dollars of Intel CapEx can generate enough chips to support $100 billion in annual revenue for AI model companies. The industry has shifted from vertical integration 30-40 years ago to horizontal specialization, but hyperscalers and model companies now design their own chips and have sufficient capital to potentially fund entire fabs. This represents a move toward pseudo-vertical integration where companies guarantee their own supply chains.
Semiconductor foundries exhibit the purest form of scale economics due to extremely high fixed costs—approximately 80% of the cost structure is fixed once a fab is built. This makes every percentage point of utilization and yield improvement disproportionately valuable. The industry has consolidated from approximately 20 foundries 40 years ago to only three advanced node foundries today.
TSMC ships upwards of 3X more leading-edge wafers than Intel. Intel acknowledges being behind in scale but claims to be within a few percent of TSMC in technology performance, power, and area density. The company argues that being within a few percent makes benchmarking less meaningful than execution quality, yield consistency, and on-time delivery for supporting large, rapid production ramps.
Intel disputes SemiAnalysis benchmarking suggesting 14A (2028) transistor density would be comparable to TSMC's N2. The company emphasizes that competitiveness depends on multiple transistor types including low-leakage and high-performance variants, different SRAM configurations, and analog/RF circuits—not just raw density metrics.
TSMC plans approximately $50 billion in CapEx while Intel targets around $20 billion. The comparison is considered unfair since TSMC serves external customers while Intel's foundry primarily serves internal needs, though Intel plans to expand external foundry services.
Intel exited DRAM in the late 1960s and sold its flash memory business a couple years ago. With hindsight, these exits appear poorly timed given AI-driven demand growth in both compute and memory. The current supply crunch for memory exceeds that for compute.
Marginal production increases can occur relatively quickly within 12-month timeframes, but production levels through 2030 will remain close to current forecasts unless the entire supply chain—including equipment suppliers and sub-suppliers—ramps up significantly. Tool lead times of 18 months mean orders placed today would not deliver until 2028, with new fab construction extending timelines to the end of the decade.
Elon Musk has publicly discussed building his own fab due to enormous demand for silicon in compute and memory. The partnership aims to accelerate fab development through collaboration, though tool bottlenecks mean the total global silicon supply won't increase—new fabs primarily provide guaranteed supply access rather than additional industry capacity.
Beyond tools, fabs require substantial power, water, and consumables. While these inputs can be scaled more readily than specialized manufacturing equipment, they remain significant constraints alongside the need for additional clean room capacity.
Fab construction costs have doubled every 4-5 years over the past 20-30 years. Lithography costs, the most expensive module, are increasing at an even faster rate. High-NA EUV scanners with associated equipment currently cost approximately $400 million, raising questions about whether this cost trajectory remains economically sustainable.
The semiconductor industry is highly risk-averse because tens of billions of dollars are invested in each new process node. This risk aversion extends to questioning fundamental assumptions like clean room requirements, as any deviation risks massive productivity losses. The industry tends to follow processes established decades ago without questioning their current optimality.
Silicon transistors have evolved from planar designs through FinFETs to current gate-all-around architectures, with further developments planned. The industry roadmap for transistor evolution is well-defined with substantial ongoing research investment.
Many CPU design methodologies were established 30 years ago. While chip design offers more capacity for risk-taking than manufacturing, the current economic environment raises questions about whether existing approaches remain optimal given the capital intensity of the business.
Given tool supply constraints as the ultimate bottleneck, Intel should secure maximum capital commitments now to purchase additional manufacturing equipment. This mirrors Nvidia's approach of locking down memory and component supply through hundreds of billions of dollars in commitments, ensuring the US maintains advanced semiconductor manufacturing capacity domestically.
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