AI That Designs Its Own Chips: Ricursive's Anna Goldie and Azalia Mirhoseini
In a Nutshell
Anna Goldie and Azalia Mirhoseini of Recursive Intelligence demo their AI platform that designs chips recursively, building on their Google AlphaChip—which used deep RL for superhuman layouts in TPUs, Axion CPUs, Pixel phones, and more—to accelerate physical design and verification by 1000x via tools like a fast STA engine. Phase 1 speeds up expert workflows for faster, cheaper chips; Phase 2 democratizes full-stack design from workloads to GDS2; Phase 3 vertically integrates AI-chip co-evolution for unmatched performance. This enables a "designless" era with a Cambrian explosion of custom AI chips, featuring organic AI placements that outperform human grids and scale via compute for massive gains at frontier workloads.
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Neural nets are replacing traditional tools, with exciting applications in chip design where neural nets achieve superhuman performance in semiconductor design processes. Anna Goldie and Azalia Mirhoseini co-created AlphaChip at Google, used on multiple generations of TPU.
Anna and Azalia introduce Recursive Intelligence, focusing on AI for chip design and chip design for AI. They have collaborated for 10 years across Google Brain, Anthropic, DeepMind, with Anna starting her PhD while working full-time and Azalia joining Stanford faculty.
Thesis: Chips are the fuel for AI; use AI to design, optimize, and automate chip design, creating a recursive self-improving loop between AI and its physical substrate.
Started in 2018 with AlphaChip, a deep reinforcement learning agent generating superhuman chip layouts, published in Nature. Used in tape-out of real chips: last four generations of Google's TPU (AI accelerator), data center CPUs called Axion, Pixel phones, autonomous vehicle chips, and adopted by external companies like MediaTek.
Phase 1: Accelerate chip design process. Challenges: physical design (placing billions of standard cells or transistors and routing billions of components) and design verification (verifying logic correctness), each taking up to a year with hundreds or thousands of human experts. High stakes: one day delay of an Nvidia Blackwell chip costs ~$225 million in lost opportunity.
Goal: Help chip makers get to market faster, build faster, cheaper, more environmentally friendly chips.
Phase 2: Democratize chip design as a platform. Input: workload (e.g., next quad model); output: architecture accelerating that workload, full design to GDS2 clean format for fabs. Unlocks customers without large expert teams.
Phase 3: Vertical integration—build own chips, train own models, co-evolve them, serve intelligence at unmatched price/capability.
Traditional flow: from architecture design to sign-off for fabs, with human experts using commercial tools that take days per optimization iteration.
Recursive approach: Redesign tools to be 100,000x faster, enabling AI with fast iteration loops for exponential learning and co-optimization across large spaces. Co-design across stack unlocks massive performance and time-to-market improvements.
Built STA (static timing analysis) engine correlating with commercial tools at high fidelity, 1000x faster. Enables AI/RL loops with rapid feedback for optimization.
Example: Single iteration yields initial result; AI optimizes recipes for tools, achieving significantly more performance.
Enabling a designless era (like fabless enabled by TSMC), as platform for chip design. Companies focus on applications/modeling; Recursive handles compute/hardware.
Impact: Democratize chip design, enable variety/performance types. Currently few mainstream AI inference chips; need more performance via customization to workloads (e.g., frontier models, low-power, high-throughput).
Cambrian explosion of custom chips for diverse workloads.
Team mixes LLM experts (worked on Quad, Gemini, Grok) with chip design experts.
AI-generated placements show curved, organic shapes minimizing wire length and improving performance, unlike human-aligned regular placements. Shocking to physical design engineers initially, similar to AlphaChip.
Customization introduces compute-scaling knob: more compute reduces design run times, enables more performant chips.
At AI workload scales, economies of scale apply. Even 1% improvement for frontier model chip is massive gain. Different scales yield different performance gains; using compute for automation/better performance.
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